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IS75V16F128GS32
3.0 Volt Multi-Chip Package (MCP) -- 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM MCP FEATURES
* Power supply voltage 2.7V to 3.3V * High performance:
Flash: 70ns maximum access time PSRAM: 65ns maximum access time
ISSI
PRELIMINARY INFORMATION MARCH 2003
(R)
* Erase Algorithms:
Automatically preprograms/erases the flash memory entirely, or by sector
* Program Algorithms:
Automatically writes and verifies data at specified address
* Package: 107-ball BGA * Operating Temperature: -30C to +85C
* Hidden ROM Region:
FLASH FEATURES * Power Dissipation:
Read Current at 1 Mhz: 4 mA maximum Read Current at 5 Mhz:18 mA maximum Sleep Mode: 5 A maximum * User Configurable Banks Flash 1 (64 Mbit) Bank A1: 8Mbit (8KB x 8 and 64KB x 15) Bank B1: 24Mbit (64KB x 48) Bank C1: 24Mbit (64KB x 48) Bank D1: 8Mbit (8KB x 8 and 64KB x 15) Flash 2 (64 Mbit) Bank A2: 8Mbit (8KB x 8 and 64KB x 15) Bank B2: 24Mbit (64KB x 48) Bank C2: 24Mbit (64KB x 48) Bank D2: 8Mbit (8KB x 8 and 64KB x 15) User chooses two virtual banks from a combination of four physical banks * Simultaneous R/W Operations (dual virtual bank): Zero latency between read and write operations; Data can be programmed or erased in one bank while data is simultaneously being read from the other bank
256 byte with a Factory-serialized secure electronic serial number (ESN), which is accessible through a command sequence
* Data Polling and Toggle Bit:
Detects the completion of the program or erase cycle
* Ready-Busy Outputs (RY/BY)
Detection of program or erase cycle completion for each flash chip
* Over 100,000 write/erase cycles * Low supply voltage (Vccf 2.5V) inhibits writes * WP/ACC input pin:
If VIL, allows partial protection of boot sectors If VIH, allows removal of boot sector protection If Vacc, program time is improved
PSRAM FEATURES (32 Mb density) * Power Dissipation:
Operating: 25 mA maximum Standby: 110 A maximum
* Chip Selects: CE1r, CE2r * Power down feature using CE2r
Sleep Mode: 10 A maximum Nap: 65 A maximum 8 mbit Partial: 80 A maximum
* Low-Power Mode:
A period of no activity causes flash to enter a low-power state
* Erase Suspend/Resume:
Suspends of erase activity to allow a read in the same bank
* Data retention supply voltage: 2.1 V to 3.3V * Byte data control: LB (DQ0-DQ7), UB
(DQ8-DQ15)
* Sector Erase Architecture:
16 sectors of 4K words each and 126 sectors of 32K words each in Word mode. Any combination of sectors, or the entire flash can be simultaneously erased
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. FlexBankTM is a trademark of Fujitsu Limited, Japan. Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 03/24/03
1
IS75V16F128GS32
GENERAL DESCRIPTION
ISSI
(R)
This 107-ball MCP is a space-saving combination of 3 memories: two 64Mbit Flash and one 32Mbit Pseudo SRAM. Each 64Mbit Flash (Flash1 and Flash 2) contains 4,194,304 words and the 32Mbit PSRAM contains 2,097,152 words. Each word is 16 bits wide. Data lines DQ0-DQ15 handle the access for all three memories. Write Enable, Output Enable, and A0-A20 are shared among the three memories. Single Byte data on the PSRAM can be accessed one at a time on DQ0-DQ7 or DQ8-DQ15 by using LB or UB, respectively. The package uses a 3.0V power supply for all operations. No other source is required for program and erase operations. The flash can be programmed in system using this 3.0V supply, or can be programmed in a standard EPROM programmer. The flash chips are compatible with the JEDEC Flash command set standard. The flash access time is 70ns and the PSRAM access time is 65ns. Each Flash memory implements an architecture composed of two virtual banks that allows simultaneous operation on each bank. Optimized performance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read from the other bank. Both operations would then be operating simultaneously on the same chip, with zero latency.
MCP BLOCK DIAGRAM
VCCf1 GND A0-A21 RESET1 CEf1 RY/BY1 64-MBIT Flash Memory (Flash 1)
VCCf2 GND A0-A21 A0-A21 WP/ACC RESET2 CEf2 RY/BY2 32-MBIT Flash Memory (Flash 2) DQ0-DQ15
VCCr A0-A20
GND
LB UB WE OE CE1r CE2r PE
32-MBIT PSRAM
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
ISSI
(R)
PIN CONFIGURATION (128 Mb Flash and 32 Mb PSRAM) PACKAGE CODE: B 107 BALL FBGA (Top View) (9.00 mm x 10.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K L M
NC NC NC NC NC NC NC NC NC NC NC NC NC
GND RY/BY2 CEf2
NC NC NC NC NC
NC NC NC NC NC NC NC NC NC
A7 A6 A5 A4
LB WP/ACC WE
A8
A11 NC A12 A15 A13 A21 A14 PE NC A16
A3 A2 A1 A0
CEf1
UB RESET1 CE2r A19 A18 RY/BY1 A20 A17
DU DU DU DU
A9 A10 DQ6
GND DQ1 OE
DQ9
DQ3 DQ4 DQ13 DQ15 Vccf1
CE1r DQ0 DQ10 Vccf1 Vccr DQ12 DQ7 GND
Shared
NC
DQ8 DQ2 DQ11 NC
DQ5 DQ14 NC
NC NC NC NC
NC
Flash Only
NC RESET2 GND Vccf2 NC
NC
NC
PSRAM Only
NC
PIN DESCRIPTIONS
A0-A20 A21 DQ0-DQ15 RESET1 RESET2 CE1r, CE2r CEf1 CEf2 OE WE PE Address Inputs, Common Address Input, Both Flash Data Inputs/Outputs, Common Reset, Flash1 Reset, Flash2 Chip Enable, PSRAM Chip Enable, Flash1 Chip Enable, Flash2 Output Enable, Common Write Enable, Common Partial Enable, PSRAM LB UB WP/ACC RY/BY1 RY/BY2 NC DU Vccf1 Vccf2 Vccr GND Lower-byte Control, PSRAM Upper-byte Control, PSRAM Write Protect/Acceleration Pin, Both Flash Ready/Busy Output , Flash1 Ready/Busy Output , Flash2 No Connection Do Not Use Power, Flash1 Power, Flash2 Power, PSRAM Ground, Common
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
3
IS75V16F128GS32
DEVICE BUS OPERATION
ISSI
H H H L H L H L H H H H X H L H H H H H H L L L L X H H H H H H H H H H H H X X H H H L L H H L H H H X X H H H H H L L H L L L X X X X X X X X X L
(9)
(R)
OPERATION(1,2) CEf1 CEf2 CE1r CE2r OE WE LB s UB s PE A21-A0 DQ7-DQ0 DQ15-DQ8 RESET1 RESET2 WP WP/ACC(12)
Full Standby Output Disable
(3)
H H L H
X X X X X X X X L
(9)
H H H H
X X X X
(10)
High-Z
High-Z
H H H H H H H H H H H H VID
H H H H H H H H H H H H X
X X X X X X X X X X X X X
High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT DIN DIN DOUT DIN High-Z DIN X DOUT DOUT DIN DIN DOUT DIN DIN High-Z X
Read from FLASH 1(4)L Read from FLASH 2(4)H Write to FLASH 1 L Write to FLASH 2 Read from PSRAM Write to PSRAM
(5)
H Valid H Valid H Valid H Valid H Valid H Valid H Valid H Valid X X
H H H H H
L H L X
L L H X
FLASH 1Temporary Sector Group X (6) Unprotection FLASH 2 Temporary Sector Group X Unprotection(6) FLASH 1 Hardware Reset FLASH 2 Hardware Reset Boot Block Sector Write Protection PSRAM Power(7) Down Program PSRAM No Read PSRAM Power Down(8) X X X H H X
X
X
X
X
X
X
X
X
X
X
X
X
VID
X
X X X H H X
H H X H L X
H H X H H L
X X X X L X
X X X X H X
X X X X H X
X X X X H X
X X X L
X X X Valid
High-Z High-Z X
High-Z High-Z X
L X X H H X
X L X H H X
X X L X X X
High-Z High-Z High-Z X High-Z X
H Valid X X
Legend : L = VIL, H = VIH, X = VIL or VIH. See "DC CHARACTERISTICS" for voltage levels. Notes:
1. Other operations except for indicated this column are prohibited. 2. Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once. 3. PSRAM Output Disable condition should not be kept longer than 1ms. 4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 5. PSRAM LB,UB control at Read operation is not supported. 6. It is also used for the extended sector group protections. 7. The PSRAM Power Down Program can be performed one time after compliance of Power-UP timings and it should not be reprogrammed after regular Read or Write. 8. PSRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IPDr current and data retention depends on the selection of Power Down Program. 9. Either or both LB and UB must be Low for PSRAM Read Operation. 10. Can be either VIL or VIH but must be valid before Read or Write. 11. See " PSRAM Power Down Program Key Table " located in the next page. 12. Protect " outer most " 2x8K bytes ( 4 words ) on both ends of the boot block sectors.
4
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
ABSOLUTE MAXIMUM RATINGS(1,5)
Rating Symbol Tstg TA VIN,VOUT VCCf1,VCCf2 VCCr VIN VACC Notes: Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All Pins(2) VCCf Supply
(2)
ISSI
Min. -55 -30 -0.3 -0.3 -0.3 -0.5 -0.5 Max. +125 +85 VCC + 0.3(6) 3.5 3.5 +13.0 +10.5 Unit C C V V V V V
(R)
VCCr Supply(2) RESET1, RESET2(3) WP/ACC
(4)
1. Voltage is defined on the basis of GND = 0 V. 2. Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot GND to -1.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf1+ 0.3V , VCCf2+ 0.3V or VCCr + 0.3 V. During voltage transitions, input or I/O pins may overshoot to VCCf1+ 2.0V , VCCf2+ 2.0 V or VCCr + 1.0 V for periods of up to 20 ns. 3. Minimum DC input voltage on RESET1 or RESET2 pin is -0.5 V. During voltage transitions, RESET1 or RESET2 pin may undershoot GND to -2.0 V for periods of up to 20 ns. The voltage difference between input and supply voltage (VIN-VCCf1 or VCCf2) does not exceed 9.0 V. The maximum DC input voltage on the RESET pin is +13.0 V that may overshoot to +14.0 V for periods of up to 20 ns. 4. Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot GND to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf1 or VCCf2 is applied. 5. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 6. This Vcc refers to the minimum of VCCf1, VCCf2, or Vccr .
RECOMMENDED OPERATING CONDITIONS
Rating Symbol TA VCCf1,VCCf2 VCCr Note:
Voltage is defined on the basis of GND = 0 V.
Parameter Ambient Temperature VCCf Supply Voltages VCCr Supply Voltages
Min. -30 2.7 2.7
Max. +85 3.3 3.3
Unit C V V
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
5
IS75V16F128GS32
DC CHARACTERISTICS
Symbol ILI ILO ILIT ICC1f Parameter Input Leakage Output Leakage RESET Inputs Leakage Current FLASH Vcc (1) Active Current (Read) Test Conditions VIN=GND to VCCf, VCCr VOUT=GND to VCCf, VCCr VCCf=VCCf max., RESET = 12.5V CEf=VIL, OE=VIH tCycle = 5Mhz Min. -1.0 -1.0 -- -- -- -- -- Typ. -- -- -- -- -- -- --
ISSI
Max. +1.0 +1.0 35 18 4 35 53
(R)
Unit A A A mA mA mA mA
ICC2f ICC3f
ICC4f
ICC5f
IACC ICC1r
ISB1f
tCycle = 1Mhz FLASH Vcc Active(2) CEf=VIL, Current(Program/Erase) OE=VIH FLASH Vcc Active(5) CEf=VIL, Current OE=VIH (Read-While-Program) FLASH Vcc Active(5) CEf=VIL, Current OE=VIH (Read-While-Erase) FLASH Vcc Active CEf=VIL, Current OE=VIH (Erase-Suspend-Program) WP/ACC Acceleration VCCf = Vcc max, Program Current WP/ACC = VACC max PSRAM Vcc Active VCCr = Vccr max, trc / twc = min Current CE1r=VIL, CE2r=VIH, VIN=VIH or VIL, trc / twc = 1 s IOUT=0 mA FLASH Vcc VCCf = Vccf max, CEf= VCCf + 0.3V, (7) Standby Current RESET = VCCf + 0.3V, WP/ACC = VCCf + 0.3V FLASH Vcc (7) Standby Current (RESET) FLASH Vcc (3,7) Current (Automatic Sleep Mode) PSRAM Vcc Standby(8) Current PSRAM VCC Power Down Current (Sleep Mode) PSRAM VCC Power (8) Down Current (Nap Mode) VCCf = Vccf max, RESET= GND + 0.3V, WP/ACC = VCCf + 0.3V VCCf = Vccf max, CEf = GND + 0.3V, RESET = VCCf + 0.3V, WP/ACC = VCCf + 0.3V, VIN = VCCf + 0.3V OR GND + 0.3V VCCr = Vccr max, CE1r VCCr -0.2V, CE2r VCCr -0.2V, VIN 0.2 V or VIN VCCr -0.2V VCCr = VCCr max., CE1r VCCr - 0.2 V CE2r 0.2 V, VIN Cycle time = tRC min VCCr = VCCr max., CE1r VCCr - 0.2 V CE2r 0.2 V, VIN Cycle time = tRC min
--
--
53
mA
--
--
40
mA
-- -- -- -- 1
-- -- --
20 25 3 5
mA mA mA A
ISB2f
--
1
5
A
ISB3f
--
1
5
A
ISB1r
--
--
110
A
IPDSr
--
--
10
A
IPDNr
--
--
65
A
6
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
DC CHARACTERISTICS (Continued)
Symbol Parameter IPD8r Test Conditions Min. Typ.
ISSI
Max. 80 Unit
(R)
VIL VIH VIH VID VACC
VOL VOH VOL VOH VLKO Notes:
PSRAM VCC Power VCCr = VCCr max., -- -- Down Current CE1r VCCr - 0.2 V (8M Partial)(8) CE2r 0.2 V, VIN Cycle time = tRC min Input Low Level -0.3 -- Input High Level (FLASH 1 or FLASH 2 ) VCCf X 0.75 -- Input High Level (PSRAM) VCCr X 0.75 -- Voltage for Sector Protection 11.5 -- and Temp. Unprotection(RESET)(4) Voltage for WP/ACC 8.5 9.0 Sector Protection/Unprotection and Program Acceleration (4) Output Low Level VCCr = VCCr min., VCCS=VCCS min. -- -- (PSRAM) IOL = 1.0 mA Output High Level VCCr = VCCr min., VCCS=VCCS min. 2.2 -- (PSRAM) IOH = -0.5 mA Output Low Level VCCf = VCCf min., VCCS=VCCS min. -- -- (Flash) IOL = 4.0 mA Output High Level VCCf = VCCf min., VCCS=VCCS min. VCCf - 0.4 -- (Flash) IOH = -0.1 mA FLASH Low Vccf 2.3 2.4 Lock-Out Voltage
A
0.5 VCCf + 0.3 VCCr + 0.3 12.5 9.5
V V V V V
0.4 -- 0.45 -- 2.5
V V V V V
1. ICC current listed includes both the DC operating current and the frequency dependent component. 2. ICC active while Embedded Algorithm (program or erase) is in progress. 3. Automatic sleep mode enables the low power mode when address remains stable for 150 ns. 4. Applicable for only VCCf applying. 5. Embedded Algorithm (program or erase) is in progress. (@5 MHz) 6. ISB2 r depends on VIN cycle time. Please refer to "APPENDIX A". 7. Standby current listed is for each FLASH chip. 8. Standby and Power down currents are reduced with Vccr < 3.0 V .
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
7
IS75V16F128GS32
AC CHARACTERISTICS - CE TIMING
Parameter CEf Recover Time CEf Hold Time CE1r High to WE Invalid time for Standby Entry Symbol Condition -- -- -- Min Max 0 3 10 -- -- --
ISSI
Unit ns ns ns
(R)
tCCR tCHOLD tCHWX
TIMING DIAGRAM FOR ALTERNATING PSRAM TO FLASH 1 OR FLASH 2
CEf
tCCR CE1r
tCCR
WE
tCHWX tCCR tCHOLD tCCR
CE2r
8
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH 1 or FLASH 2
Sector Bank
Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B
ISSI
Sector K-Word
4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
(R)
Address
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35
Address
000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h
Bank
Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank C
Address
SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71
K-Word
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address
0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 200000h 9
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
ISSI
Sector K-Word
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
(R)
FLEXIBLE SECTOR-ERASE ARCHITECTURE ON FLASH 1 or FLASH 2 (Continued)
Sector Bank
Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C
Address
SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106
Address
208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h
Bank
Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D
Address
SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
K-Word
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4
Address
320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3F9000h 3FA000h 3FB000h 3FC000h 3FD000h 3FE000h 3FF000h
10
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
USER CONFIGURABLE BANK ARCHITECTURE TABLE - FLASH 1 or FLASH 2 Virtual Bank 1
Bank Split Choice 1 Choice 2 Choice 3 Choice 4 Volume 8 Mbit 24 Mbit 24 Mbit 8 Mbit Combination Bank A Bank B Bank C Bank D Volume 56 Mbit 40 Mbit 40 Mbit 56 Mbit
ISSI
Virtual Bank 2
Combination Bank B, C, D Bank A, C, D Bank A, B, D Bank A, B, C
(R)
EXAMPLE OF VIRTUAL BANKS COMBINATION TABLE - FLASH 1 or FLASH 2 Virtual Bank 1
Bank Split Volume Choice 1 8 Mbit Combination Bank A Sector Size 8x4 Kword 15x32 Kword Choice 2 16 Mbit Bank A,D 16x4 Kword 30x32 Kword Choice 3 24 Mbit Bank B 48x32 Kword 40 Mbit Bank A, C, D 16x4 Kword 78x32 Kword Choice 4 Notes:
1) When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, if erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out. They would output the sequence flag once they were selected. Meanwhile the system would get to read from either Bank C or Bank D. 2) Each word is made-up of 2 bytes: one upper byte and one lower byte. A KWord is 210 words.
Virtual Bank 2
Volume 56 Mbit Combination Bank B, C, D Sector Size 8x4 Kword 111x32 Kword 48 Mbit Bank B,C 96x32 Kword
32 Mbit
Bank A,B
8x4 Kword 63x32 Kword
32 Mbit
Bank C,D
8x4 Kword 63x32 Kword
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
11
IS75V16F128GS32
SIMULTANEOUS OPERATION TABLE - FLASH 1 or FLASH 2
Case
1 2 3 4 5 6 7 Note:
ISSI
Virtual Bank 1 Status
Read Mode Read Mode Read Mode Read Mode Autoselect Mode Program Mode Erase Mode
(1)
(R)
Virtual Bank 2 Status
Read Mode Autoselect Mode Program Mode Erase Mode (1) Read Mode Read Mode Read Mode
1) By writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. 2) Bank 1 and Bank 2 are divided for the sake of convenience at Simultaneous Operation. Actually, the Bank consists of 4 banks, Bank A, Bank B, Bank C, and Bank D. Bank Address (BA) means to specify each of the Banks.
12
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2
Bank Address Bank
Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank A Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B
ISSI
Sector Address Address Range Word Mode
000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh
(R)
Sector
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X
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13
IS75V16F128GS32
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 (Continued)
Bank Address Bank
Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B Bank B
ISSI
Sector Address Address Range Word Mode
0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh
(R)
Sector
SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
14
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 (Continued)
Bank Address Bank
Bank B Bank B Bank B Bank B Bank B Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C
ISSI
Sector Address Address Range Word Mode
1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh
(R)
Sector
SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
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15
IS75V16F128GS32
SECTOR ADDRESS TABLE - FLASH 1 or FLASH 2 (Continued)
Bank Address Bank
Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank C Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D Bank D
ISSI
Sector Address Address Range Word Mode
2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh 370000h to 377FFFh 378000h to 37FFFFh 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3F8FFFh 3F9000h to 3F9FFFh 3FA000h to 3FAFFFh 3FB000h to 3FBFFFh 3FC000h to 3FCFFFh 3FD000h to 3FDFFFh 3FE000h to 3FEFFFh 3FF000h to 3FFFFFh
(R)
Sector
SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1
16
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
SECTOR ADDRESS GROUP TABLE - FLASH 1 or FLASH 2 Sector
SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32
ISSI
Sectors
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 to SA10 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X
(R)
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
17
IS75V16F128GS32
SECTOR ADDRESS GROUP TABLE - FLASH 1 or FLASH 2 (Continued) Sector
SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47
ISSI
Sectors
SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 X X X X X X 0 0 1 1 1 1 1 1 1 1 1 X X X X X X 0 1 0 1 1 1 1 1 1 1 1 X X X X X X X 0 0 0 0 1 1 1 1 X X X X X X X 0 0 1 1 0 0 1 1 X X X X X X X 0 1 0 1 0 1 0 1
(R)
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FLASH MEMORY AUTOSELECT CODES TABLE - FLASH 1 or FLASH 2
Type Manufacturer's Code Device Code Extended Device Code
(2)
A21 to A12 BA BA BA BA Sector Group Address
A6 L L L L L
A3 L L H H L
A2 L L H H L
A1 L L H H H
A0 L H L H L
Code (HEX) 04h 227Eh 2202h 2201h 01h(1)
Sector Group Protection Notes:
Legend: L = VIL, H = VIH. See " DC CHARACTERISTICS" for voltage levels. 1. Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. 2. A read cycle at address (BA) 01h outputs device code. When 227Eh was output, this indicates that there will require two additional codes, called Extended Device Codes. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh. .
18
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
FLASH MEMORY COMMAND DEFINITIONS - FLASH 1 or FLASH 2
Command Sequence
Bus Write Cycle Req'd First Bus Cycle Second Bus Write Cycle Third Bus Write Cycle Fourth Bus Read/Write Fifth Bus Cycle
ISSI
Sixth Bus Cycle
(R)
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Read / Reset
(1)
1
XXXh
F0h
--
--
--
--
--
--
--
--
--
--
Read / Reset (1)
3
555h
AAh
2AAh
55h
555h (BA) 555h
F0h
RA
RD
--
--
--
--
Autoselect
3
555h
AAh
2AAh
55h
90h
--
--
--
--
--
--
Program
4
555h
AAh
2AAh
55h
555h
A0h
PA
PD
--
--
--
--
Program Suspend
1
BA
B0h
--
--
--
--
--
--
--
--
--
--
Program Resume
1
BA
30h
--
--
--
--
--
--
--
--
--
--
Chip Erase
6
555h
AAh
2AAh
55h --
555h
80h
--
555h
AAh -- AAh
2AAh
55h -- 55h
555h
10h
--
--
555h
--
2AAh
Sector Erase
6
555h
AAh
2AAh
55h
555h
80h
SA
30h
Erase Suspend
1
BA
B0h
--
--
--
--
--
--
--
--
--
--
Erase Resume Extended Sector Group Protection
(3)
1
BA
30h 60h
--
--
--
--
--
--
--
--
--
--
4
XXXh
SGA
60h
SGA
40h
SGA
SD
--
--
--
--
Set to Fast Mode (2) Fast Program
(2)
3
555h
AAh
2AAh
55h
555h
20h
--
--
--
--
--
--
2
XXXh
A0h
PA
PD (6) F0H
--
--
--
--
--
--
--
--
-- --
Reset from Fast Mode (2) Query
(4)
2
BA (BA) 55h 555h
90h
XXXh
--
--
--
--
--
--
--
1
98h
--
--
--
--
--
--
--
--
--
Hi-ROM Entry Hi-ROM Program Hi-ROM Exit (5)
3
AAh AAh AAh
2AAh
55h
555h
88h
--
--
--
--
--
--
(5)
4
555h
2AAh 2AAh
55h
555h
(HRBA)
A0h
(HRA) PA
XXXh
PD
--
--
--
--
4
555h
55h
555h
90h
00h
--
--
--
--
Notes: 1. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 2. This command is valid during Fast Mode. 3. This command is valid while RESET = VID 4. The valid address is A6 to A0. 5. This command is valid during Hi-ROM mode. 6. The data "00h" is also acceptable.
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
19
IS75V16F128GS32
FLASH MEMORY COMMAND DEFINITIONS - FLASH 1 or FLASH 2 (Continued)
Notes: * Address bits A21 to A11 = X = "H" or "L" for all address commands except or Program Address (PA), Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA).
ISSI
* SPA = Sector group address to be protected.
Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0). SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses.
(R)
* Bus operations are defined in "DEVICE BUS
OPERATIONS".
* RA = Address of the memory location to be read
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse.
* HRA = Address of the Hi-ROM area :
000000h to 00007Fh HRBA = Bank Address of the Hi-ROM area (A21 = A20 = A19 = VIL)
* SA = Address of the sector to be erased. The
combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A21, A20, A19)
* The system should generate the following address
patterns : 555h or 2AAh to addresses A10 to A0
* Both Read/Reset commands are functionally
equivalent, resetting the device to the read mode.
* RD = Data read from location RA during read
operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of the write pulse.
* Command combinations not described in FLASH
Memory Command Definitions are illegal.
20
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
FLASH READ ONLY OPERATIONS CHARACTERISTICS - FLASH 1 or FLASH 2
JEDEC Symbol Standard Symbol
ISSI
Condition Min Max 70 CEf = VIL, OE = VIL OE = VIL -- -- -- -- -- 0 -- 70 70 30 25 25 -- Unit ns ns ns ns ns ns ns
(R)
Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode Test Conditions:
Output Load : 1 TTL gate and 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or VCCf Timing measurement reference level Input : VCCf/2 Output : VCCf/2
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX
--
tRC tACC tCE tOE tDF tDF tOH tREADY
--
20
s
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
21
IS75V16F128GS32
FLASH READ CYCLE - FLASH 1 or FLASH 2
tRC Address
Address Stable
ISSI
(R)
tACC CEf1
tOE OE
tDF
tOEH
WE
High-Z
tCE
Output valid
tOH
High-Z
DQ
22
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
ISSI
tRC
(R)
FLASH HARDWARE RESET / READ OPERATION TIMING DIAGRAM - FLASH 1 or FLASH 2
Address
Address Stable
tACC CEf1 tRH
tRP
tRH
tCE
RESET
tOH
High-Z Output valid
DQ
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
23
IS75V16F128GS32
FLASH WRITE/ERASE/PROGRAM OPERATIONS - FLASH 1 or FLASH 2
JEDEC Symbol tAVAV tAVWL Standard Symbol tWC tAS tASO tAH tAHT tDS tDH tOEH tOEH tCEPH tOEPH tGHWL tGHEL tWS tCS tWH tCH tWP tCP tWP tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP
ISSI
Min 70 0 12 45 0 30 0 0 10 20 20 0 0 0 0 0 0 35 35 25 25 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns s s
(R)
Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Output Enable Hold Time Toggle and Data Polling CEf High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE to CEf) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CEf Setup Time (WE to CEf) WE Hold Time (CEf to WE) CEf Hold Time (WE to CEf) Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Word Programming Operation (1) Sector Erase Operation VCC Setup Time Rise Time to VID (2) Rise Time to VACC
(3) (1)
--
tWLAX
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
6 0.5
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
100 2.0
--
tDVWH tWHDX
-- -- -- --
tGHWL tGHEL tWLEL tELWL tEHWH tWHEH tWHWL tELEH tWHWL tEHEL tWHWH1 tWHWH2
-- --
50 500 500 4 100
Voltage Transition Time (2) Write Pulse Width (2)
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
ISSI
JEDEC Symbol
(2)
(R)
FLASH WRITE/ERASE/PROGRAM OPERATIONS - FLASH 1 or FLASH 2 (Continued)
Standard Symbol tOESP tCSP tRB tRP tRH tBUSY tEOE tTOW tSPD
Parameter OE Setup Time to WE Active CEf Setup Time to WE Active (2) Recover Time from RY/BY RESET Pulse Width RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-Out Time Erase Suspend Transition Time Notes:
1. Does not include preprogramming time. 2. For Sector Group Protection operation. 3. For Accelerated Program operation.
Min 4 4 0 500 200
Typ
Max
Unit s s ns ns ns ns ns s s
-- -- -- -- -- -- -- -- --
-- --
50
--
-- -- -- -- -- -- -- -- --
-- -- -- -- --
90 70
--
20
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
25
IS75V16F128GS32
FLASH WRITE CYCLE - FLASH 1 or FLASH 2
(WE CONTROL)
ISSI
3rd Bus Cycle 555h PA Data Polling PA
(R)
tRC
ADDRESS
tWC
tAS
tAH
CEf
tCS
tCH
tCE
OE tGHWL WE
tWP
tWPH
tWHWH1
tOE
tDS
A0h
tDH PD
DQ7 Dout
tDF
Dout
tOH
DQ
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence.
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
FLASH WRITE CYCLE - FLASH 1 or FLASH 2
(CEf CONTROL)
ISSI
3rd Bus Cycle Data Polling PA PA
(R)
ADDRESS
555h
tWC CEf1 tWS OE tGHEL WE tDS DQ
A0h
tAS
tAH
tWH
tCP
tCPH
tWHWH1
tDH PD
DQ7 Dout
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles out of four bus cycle sequence.
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
27
IS75V16F128GS32
ISSI
*
(R)
FLASH AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS - FLASH 1 or FLASH 2
ADDRESS
555h tWC
2AAh tAS tAH
555h
555h
2AAh
SA
CEf1
tCH tCS
OE
tGHWL
tWP tWPH
WE
tDS tDH
AAh 55h 30h for Sector Erase
DQ
tVCS
80h
AAh
55h
10h/ 30h
Vccf
Notes: 1. SA is the sector address for Sector Erase. Address = 555h for Chip Erase.
28
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
FLASH AC WAVEFORMS FOR DATA POLLING DURING EMBEDDED ALGORITHM OPERATIONS - FLASH 1 or FLASH 2
ISSI
(R)
CEf1
tCH tOE tDF
OE
tOEH
WE
tCEf1
(1)
DQ
Data In
DQ7 tWHWH1 or 2
DQ7 = Valid Data
High - Z
DQ0/DQ6
Data In
DQ0 to DQ6 = Output Flag
DQ0 to DQ6 Valid Data
High - Z
tBUSY
tEOE
RY/BY
Notes: 1. DQ7 = Valid Data (the device has completed the Embedded operation.)
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
29
IS75V16F128GS32
ISSI
(R)
FLASH AC WAVEFORMS FOR TOGGLE BIT DURING EMBEDDED ALGORITHM OPERATIONS - FLASH 1 or FLASH 2
ADDRESS
tAHT tASO tAHT tAS
CEf1
tCEPH
WE
tOEH tOEPH tOEH
OE
tDH tOE
Toggle Data Toggle Data
tCEf
(1)
DQ6/DQ2
Data
Toggle Data
Stop Toggle
Output Valid
tBUSY
RY/BY
Notes: 1. DQ6 stops toggling (the device has completed the Embedded operation).
30
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
FLASH BACK-to-BACK READ/WRITE TIMING DIAGRAM - FLASH 1 or FLASH 2
ISSI
Read tRC Command tWC BA2 (555h) tAS tAH Read tRC BA1 tACC tCE tAHT Command tWC BA2 (PA) Read tRC BA1 Read tRC BA2 (PA) tAS
(R)
ADDRESS
BA1
CEf1
tOE tCEPH
OE
tGHWL tWP tOEH tDF
WE
tDS tDH tDF Valid Output Valid Input (PD) Valid Output Status
DQ
Valid Output
Valid Input (A0h)
Note: 1. This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Virtual Bank 1. BA2: Address of Virtual Bank 2.
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
31
IS75V16F128GS32
BY FLASH RY/BY TIMING DIAGRAM DURING WRITE/ERASE OPERATIONS - FLASH 1 or FLASH 2
ISSI
(R)
CEf
The rising edge of the last write pulse
WE
Entire programming or erase operations
RY/BY
tBUSY
FLASH RESET, RY/BY TIMING DIAGRAM - FLASH 1 or FLASH 2 BY
WE
RESET
tRP
tRB
RY/BY
tREADY
32
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
FLASH TEMPORARY SECTOR GROUP UNPROTECTION - FLASH 1 or FLASH 2
ISSI
(R)
VCCf tVCS VID 3V RESET CEf1
tVIDR
tVLHT
WE tVLHT RY/BY Unprotection Period Program or Erase Command Sequence tVLHT
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33
IS75V16F128GS32
FLASH ACCELERATED PROGRAM - FLASH 1 or FLASH 2
ISSI
(R)
VCCf VACC VIH WP/ACC CEf1
tVCS
tVACCR
tVLHT
WE
tVLHT
RY/BY
Program Command Sequence
tVLHT
Acceleration Period
34
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
FLASH EXTENDED SECTOR GROUP PROTECTION- FLASH 1 or FLASH 2
ISSI
(R)
tVCS
Vccf
tVLHT RESET tVIDR
SPAX SPAX SPAY
tWC
tWC
Address A6, A3 A2, A0 A1 CEf1 OE WE
tWP
TIME-OUT
Data
60h
60h
40h
01h
60h
tOE
Notes: 1. SPAX : Sector Group Address to be protected, SPAY : Next Group Sector Address to be protected, TIME-OUT: Time-Out window = 250 s (Min)
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
35
IS75V16F128GS32
FLASH ERASE AND PROGRAMMING PERFORMANCE - FLASH 1 or FLASH 2
Parameter Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle Note:
1. Typical Erase conditions TA = 25C, VCCf_1 & VCCf_2 = 2.9V. Typical Program conditions TA = 25C, VCCf_1 & VCCf_2 = 2.9V. Data= Checker
ISSI
Min. -- -- -- 100,000 Typ.(1) 0.5 6.0 -- -- Max. 2.0 100 200 -- Unit s s s cycle Remarks Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead
(R)
36
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
PSRAM POWER DOWN PROGRAM KEY TABLE
Basic KEY Table
ISSI
A16 A17 A18 A19 A20
(R)
Definition
KEY
Mode Select
Area Select
A18 L L H H
A19 L H L H
A20 L X X H
AREA BOTTOM
(3)
RESERVED RESERVED TOP
(2)
A16 L L H H Available KEY Table
A17 L H H H
MODE NAP (4) RESERVED 8M Partial
(4,5)
SLEEP
A16 MODE
A17
A18
A19 Area Select
A20
Data Retention Area
Mode Select
NAP L H 8M Partial H SLEEP H L H H X L L X L
X L H X
X L H X
None Bottom 8M Only Top 8M only None
Notes: 1: The Power Down Program can be performed one time after compliance of Power-up timings and it should not be re-programmed after regular Read or Write. Unspecified addresses, A0 to A15, can be either High or Low during the programming. The RESERVED key should not be used. 2: TOP area is from the lowest address location. (i.e., A[20:0] = H)) 3: BOTTOM area is from the highest address location. (i.e., A[20:0] = L) 4: NAP and SLEEP do not retain the data and Area Select is ignored. 5: Default state. Power Down Program to this SLEEP mode can be omitted.
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
37
IS75V16F128GS32
PSRAM READ OPERATIONS
Parameter Read Cycle Time Chip Enable Access Time
(1,4) (1,3)
ISSI
Symbol tRC tCE tOE tAA tOH
(2)
(R)
Min 70
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
--
65 40 65
Output Enable Access Time(1) Address Access Time Output Data Hold Time(1) CE1r Low to Output Low-Z OE Low to Output Low-Z
(2)
-- -- --
5 5 0
tCLZ tOLZ tCHZ tOHZ
(5)
-- -- --
20 20
CE1r High to Output High-Z(2) OE High to Output High-Z
(2)
-- --
-5 25 10 -5 -10
Address Setup Time to CE1r Low Address Setup Time to OE(3,6) Address Setup Time to OE
(7)
tASC tASO tASO(ABS)
LB/UB Set up Time to CE1r Low LB/UB Set up Time to OE Low Address Invalid Time
(4)
(5)
tBSC tBSO tAX
(4)
-- -- -- -- --
5
--
70 45 -5 -5 -5 -5 25 45 12 25 12
Address Hold Time from CE1r Low
tCLAH tOLAH tCHAH tOHAH tCHBH tOHBH
Address Hold Time from OE Low(4,8) Address Hold Time from CE1r High Address Hold Time from OE High LB/UB Hold Time to CE1r Low LB/UB Hold Time to OE Low CE1r Low to OE Low Delay Time CE1r High Pulse Width OE High Pulse Width(6,8,9) OE High Pulse Width Notes:
(7) (3,6,8,9)
-- -- -- -- -- --
1000
tCLOL tOLCH tCP tOP tOP(ABS)
OE Low to CE1r High Delay Time(8)
-- --
1000
--
1. The output load is 30 pF. 2. The output load is 5 pF. 3. The tCE is applicable if OE is brought to Low before CE1r goes Low and is also applicable if actual value of both or either tASO or tCLOL is shorter than specified value. 4. Applicable only to A0 and A1 when both CE1r and OE are kept at Low for the address access. 5. Applicable if OE is brought to Low before CE1r goes Low. 6. The tASO, tCLOL (Min) and tOP (Min) are reference values when the access time is determined by tOE. If the actual value of each parameter is shorter than the specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. For example, if actual tASO, tASO (actual) , is shorter than specified minimum value, tASO (Min) , during OE control access (i.e., CE1r stays Low) , the tOE becomes tOE (Max) + tASO (Min) - tASO (actual) . 7. The tASO[ABS] and tOP[ABS] are the absolute minimum values during OE control access. 8. If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC (Min) - tCLOL (actual) or tRC (Min) - tOP (actual) . 9. Maximum value is applicable if CE1r is kept at Low.
38
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
PSRAM WRITE OPERATIONS
Parameter Write Cycle Time(1) Address Setup Time Address Hold Time
(2) (2)
ISSI
Symbol tWC tAS tAH tCS tCH tWS tWH tBS tBH tOES tOEH tOEH(ABS) tOHCL tOHAH tCW tWP tWRC tWR tDS tDH tCP
(7)
(R)
Value Min. Max. 70 0 35 0 0 0 0 -5 -5 0 25 12 -5 -5 45 45 10 10 15 0 12 -- -- -- 1000 1000 -- -- -- -- 1000 1000 -- -- -- -- -- -- 1000 -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE1r Write Setup Time CE1r Write Hold Time WE Setup Time WE Hold Time LB adnd UB Setup Time LB adnd UB Hold Time OE Setup Time(3) OE Hold Time OE Hold Time
(3,4) (5)
OE High to CE1r Low Setup Time(6) OE High to Address Hold Time CE1r Write Pulse Width WE Write Pulse Width
(1,8) (1,8)
CE1r Write Recovery Time(1,9) WE Write Recovery Time(1,3,9) Data Setup Time Data Hold Time CE1r High Pulse Width(9) Notes:
1. Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR). 2. New write address is valid from either CE1r or WE that is brought to High. 3. Maximum value is applicable if CE1r is kept at Low and both WE and OE are kept at High. 4. The tOEH is specified from end of tWC (Min), and is a reference value when access time is determined by tOE. If actual value is shorter than specified minimum value, tOE becomes longer by the amount of subtracting actual value from specified minimum value. 5. The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1r stay Low. 6. tOHCL (Min) must be satisfied if read operation is not performed prior to write operation. In case OE is disabled after tOHCL (Min), WE Low must be asserted after tRC (Min) from CE1r Low. In other words, read operation is initiated if tOHCL (Min) is not satisfied. 7. Applicable if CE1r stays Low after read operation. 8. tCW and tWP are applicable if write operation is initiated by CE1r and WE, respectively. 9. tWRC and tWR are applicable if write operation is terminated by CE1r and WE, respectively. The tWR (Min) can be ignored if CE1r is brought to High together or after WE is brought to High. In such a case, the tCP (Min) must be satisfied.
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
39
IS75V16F128GS32
PSRAM POWER DOWN PARAMETERS
Parameter CE2r Low Setup Time for Power down Entry CE2r Low Hold Time after Power down Entry CE1r High Hold Time Following CE2r High after Power down Exit SLEEP Mode only CE1r High Setup Time following CE2r High after Power down Exit (Except for SLEEP Mode) CE1r High Setup Time following CE2r High after Power down Exit CE1r High to PE Low Setup Time
(1) (1)
ISSI
Symbol tCSP tC2LP tCHH tCHHN tCHS tEPS tEP tEPH tEAS
(1)
(R)
Value Min. Max. 10 70 350 1 10 70 70 70 15 0
Unit ns ns s s ns ns ns ns ns ns
-- -- -- -- -- -- -- -- -- --
PE Power Down Program Pulse Width PE High to CE1r Low Hold Time (1) Address Setup Time to PE High
(1)
Address Setup Time from PE High
tEAH
Note: 1. Applies to Power Down Program.
PSRAM OTHER TIMING PARAMETERS
Parameter CE1r High to OE Invalid for Standby Entry CE1r High to WE Invalid for Standby Entry CE2r Low Hold Time after Power-up
(2) (1)
Symbol tCHOX tCHWX tC2LH tC2HL
(2)
Value Min. Max. 10 10 50 50 350 1
Unit ns ns s s s ns
CE2r High Hold Time after Power-up(3) CE1r High Hold Time Following CE2r High after Power-up Input Transition Time(4)
tCHH tT
-- -- -- -- --
25
Notes: 1. Unintended data may be written into any address location if tCHWX is not satisfied. 2. Must satisfy tCHH (Min) after tC2LH (Min) . 3. Requires Power Down mode entry and exit after tC2HL. 4. Input Transition Time (tT) at AC testing is 5 ns as shown below. If actual tT is longer than 5 ns, it may violate some timing parameters.
PSRAM AC TEST CONDITIONS
Parameter Input High Level Input Low Level Input Timing Measurement Level Input Transition Time 40 Symbol VIH VIL VREF tT Condition VCCr = 2.7V to 3.3V VCCr = 2.7V to 3.3V VCCr = 2.7V to 3.3V Between VIL and VIH Value 2.3 0.4 1.3 5 Unit V V V ns
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
PSRAM READ TIMING (OE Control Access)
tRC tRC ADDRESS VALID tASO tOHAH tOHAH
ISSI
ADDRESS VALID tCE
(R)
ADDRESS
CE1r
tCLOL tOE tOE tASO tOP tOHBH tBSO tOLCH
OE
tBSO
tOHBH
LB / UB
tOHZ tOLZ tOH tOLZ tOH tOHZ
DQ (Output)
VALID DATA OUTPUT VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
PSRAM READ TIMING (CE1r Control Access)
tRC tRC ADDRESS VALID tCHAH tASC tCE tCP tCHAH
ADDRESS
tASC
ADDRESS VALID tCE
CE1r
OE
tBSC
tCHBH
tBSC
tCHBH
LB / UB
tCHZ tCLZ tOH tCLZ tOH tCHZ
DQ (Output)
VALID DATA OUTPUT VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
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41
IS75V16F128GS32
PSRAM READ TIMING (Address Access after OE Control Access)
tRC tRC ADDRESS VALID (No Change)
ISSI
ADDRESS VALID
(R)
ADDRESS (A20-A3)
ADDRESS (A2-A0)
tASO
ADDRESS VALID tOLAH tAX
ADDRESS VALID tAA tOHAH
CE1r
tOE tOHZ
OE
tBSO
tOHBH
LB / UB
tOLZ
tOH
tOH
DQ (Output)
VALID DATA OUTPUT VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
PSRAM READ TIMING (Address Access after CE1r Control Access)
tRC tRC ADDRESS VALID (No Change)
ADDRESS (A20-A3)
ADDRESS VALID
ADDRESS (A2-A0)
tASC
ADDRESS VALID tCLAH tAX
ADDRESS VALID tAA tCHAH
CE1r
tCHZ tCE
OE
tCHBH tBSC
UB, LB
tCLZ tOH tOH
DQ (Output)
VALID DATA OUTPUT VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
PSRAM WRITE TIMING (CE1r Control)
tWC
ISSI
Address Valid tAS tAH tAS
(R)
Address
CE1r
tWS tCW tWH
tWRC tWS
WE
tBS tBH tBS
UB, LB
tOHCL
OE
tDS tDH
DQ (Input)
Valid Data Input
Note: CE2r and PE must be High during write cycle.
PSRAM WRITE TIMING (WE Control, Single Write Operation)
tWC
Address
tOHAH
tAS
Address Valid
tAH tCH tCP tAS
CE1r
tOHCL
tCS tWP
WE
tWR
tOHBH
tBS
tBH
UB, LB
tOES
OE
tOHz tDS tDH
DQ (Input)
Valid Data Input
Note: CE2r and PE must be High during write cycle.
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43
IS75V16F128GS32
PSRAM WRITE TIMING (WE Control, Continuous Write Operation)
tWC
ISSI
Address Valid
(R)
ADDRESS
tOHAH
tAS
tAH
tAS
CE1r
tOHCL
tCS
tWP
tWR
WE
tBH tBS
tBH
tBS
UB, LB
tOES
OE
tOHz
tDS
tDH
DQ
(Input)
Valid Data Input
Note: CE2r and PE must be High during write cycle.
PSRAM READ / WRITE TIMING (CE1r Control)
tWC
ADDRESS
tCHAH tAS
Write Address tAH tASC
Read Address
CE1r
tCP tWRC tWS tCW tWH tWS tWH tCLOL
WE
tCHBH
tBS
tBH
tBSO
UB, LB
tOHCL
OE
tCHZ tOH tDS tDH tOLz
DQ
Read Data Output Valid Data Input
Note: Write address is valid from either CE1r or WE of last falling edge. 44
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
PSRAM READ / WRITE TIMING (CE1r Control)
tRC
ISSI
Read Address
tWRC
(R)
ADDRESS
Write Address
tAS tCHAH
tASC
CE1r
tWRC (Min) tWH tWS tCE tWH tCP tWS
WE
tBH tBSC tCHBH tBS
UB, LB
tOEH tOHCL
OE
tCHZ tDH tCLZ tOH
DQ
Write Data Input
Read Data Output
Note: The tOEH is specified from the time satisfied oth tWRC and tWR(min).
PSRAM READ / WRITE TIMING (READ = OE Control, WRITE = WE Control)
tWC
ADDRESS
tOHAH tAS
Write Address tAH tASO
Read Address
CE1r WE
Low
tWP
tWR
tOEH
tOHBH
tBS
tBH
tBSO
UB, LB
tOES
OE
tOHZ
tOH
tDS
tDH
tOLZ
DQ
Read Data Output Write Data Input
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE.
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
45
IS75V16F128GS32
PSRAM READ / WRITE TIMING (READ = OE Control, WRITE = WE Control)
tRC
ISSI
Read Address tASO tOHAH tAS Write Address
(R)
Address
CE1r WE
Low tWR tOEH
tBH
tBSO
tOHBH
tBS
UB, LB
tOE tOES
OE
tOHZ tDH tOLZ tOH
DQ
Write Data Input Read Data Output
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled OE.
46
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
PSRAM POWER DOWN TIMING
ISSI
(R)
CE1r
tEPS tEP tEPH
PE
tEAS KEY tEAH
ADDRESS A20-A16
Note: CE2r must be High for Power Down Programming. Any other inputs not specified above can be either High or Low.
PSRAM STANDBY ENTRY and EXIT TIMING
CE1r
tCHS
CE2r
tCSP tC2LP tCHH (CHHN)
High - Z
DQ
Power Down Entry Power Down Mode Power Down Exit
Note: This Power Down mode can be also used for Power-up Timing #2 except that tCHHN can not be used at Power-up Timing.
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47
IS75V16F128GS32
PSRAM POWER UP TIMING 1
ISSI
(R)
CE1r tCHS tC2LH tCHH
CE2r
Vccr 0V
Vccr Min
Note: The
tC2LH specifies after Vccr reaches specfied minimum level.
PSRAM POWER UP TIMING 2
CE1r tC2HL
tCSP tC2LP
tCHS tCHH
CE2r tC2HL Vccr Min 0V
Vccr
Note: The tC2HL specifies from CE2r Low to High transition after Vccr reaches specified minimum level. CE1r must be brought to High prior to or together with CE2r Low to High transition.
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
PSRAM DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Vccr Data Retention Supply Voltage Vccr Data Retention Supply Current Conditions CE1r = CE2r VCCr -0.2V OR, CE1r = CE2r = VIH 2.1 V VCCr 2.7 V, VIN = VIH (1) or VIL CE1r = CE2r = VIH (1), IOUT = 0 MA 2.1 V VCCr 2.7 V, VIN 0.2 V or VIN VCCr -0.2 V, CE1r = CE2r VCCr -0.2 V IOUT = 0 mA 2.7 V VCCr 3.3 V, At Data Retention Entry 2.7 V VCCr 3.3 V, After Data Retention -- Min. 2.1 -- Max. 3.3 1.5
ISSI
Unit V mA
(R)
VDR IDR
IDR1
Vccr Data Retention Supply Current
--
100
A
tDRS tDRR
V/t
Data Retention SetupTime Data Retention RecoveryTime
0 200 0.2
-- -- --
ns ns V/s
VCCR Voltage Transition Time
Note: 1. 2.0 V VIN VCCr + 0.3
PSRAM DATA RETENTION TIMING
tDRS 3.3V 2.7V 2.1V CE2r CE1r 0.4V GND
Data Retention Mode Data bus must be in High-Z at data retention entry
V/t
tDRR
V/t
Vccr
CE1r = CE2r >Vccr - 0.2V or VIH(1) Min
Note:
1. 2.0 V VIH VCCr + 0.3 V
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
49
IS75V16F128GS32
PIN CAPACITANCE
Symbol CIN COUT CIN2 Parameter Input Capacitance Output Capacitance Control Pin Capacitance Conditions Min. Max. 20 25 25
ISSI
Unit pF pF pF
(R)
=0V VOUT = 0 V VIN = 0 V
VIN
Notes: 1. Test conditions TA = +25 C, f = 1.0 MHz
HANDLING OF PACKAGE:
Please handle this package carefully because the sides of the package have acute angles.
CAUTION:
1) The high voltage (VID) cannot be applied to address pins and control pins except RESET. Exception is when autoselect and sector group protection function are used. Then the high voltage (VID) can be applied to RESET. 2) Without the high voltage (VID) sector group protection can be achieved by using the "Extended Sector Group Protection" command.
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PRELIMINARY INFORMATION Rev. 00D 03/24/03
IS75V16F128GS32
MINI BALL GRID ARRAY - 107-Ball BGA PACKAGE CODE: B (9.00 mm x 10.00 mm Body, 0.8 mm Ball Pitch)
ISSI
(R)
o 0.40 + 0.10/-0.05 (107X) 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K L M 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M E1 E A1 SEATING PLANE A e
e D1 D
Symbol A A1 D D1 E E1 e
Min. 1.15 0.05 9.90 -- 8.90 -- --
Typ. 1.25 0.10 10.00 8.80 9.00 7.20 0.80
Max. 1.40 0.15 10.10 -- 9.10 -- --
Units mm mm mm mm mm mm mm
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 03/24/03
51
IS75V16F128GS32
ORDERING INFORMATION Industrial Range: -30oC to +85oC
Flash Bank Order Part No. Organization IS75V16F128GS32-7065BI User Configurable Flash Speed(ns) 70 PSRAM Speed(ns) 65
ISSI
(R)
Package 107-ball BGA
52
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 03/24/03

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